In the development of computer networks, a situation often occurs where two or more digital systems are cross-linked to each other in order to pass messages between a first system having a first domain, and a second system having a second domain. Very often, each of the Central Processing Modules in each of the first and second domains will have a cache memory for immediate access to useful data and additionally, will also have invalidation queues needful to invalidate stale data which may occur during the operation of the system. Thus, as seen in FIG. 2, a dual domain system having a first domain 10a and a second domain 10b, are cross-linked to enable communications to occur with each other.
Referring to FIG 2, there is seen the first domain 10a having a Central Processing Module (CPM) 11a connected to a cache 18a. The Central Procesing Module 11a also has an internal invalidation queue 11iqa (snoop invalidation queue) which is used to accumulate addresses which must be subsequently used to invalidate addresses and data in the cache 18a.
The Central Processing Module (CPM) 11a is connected to a local bus or first domain bus 14a designated as the SBUS. Connected to the SBUS 14a (local bus) is an Input/Output Module (IOM) 12a, a System Control Module (SCM) 13a and a Bus Exchange Module (BEM) 23ea. The system control module 13a holds an arbitration circuit (ARBIT CKT) logic unit 13ra which regulates those commands, messages or transfers that will get priority or access to the local bus 14a (SBUS). A Memory Bus 16a (MBUS) connects the System Control Module 13a to the Bus Exchange Module (BEM) 23ea, providing access to a first domain Main Memory 15a.
The second digital domain 10b of this system shows a similar arrangement where the Central Processing Module 11b having a snoop invalidation queue 11iqb within, is connected to its personal cache memory 18b. The Central Processing Module 11b connects to the remote bus 14b, designated OSBUS, which buys is connected to an Input/Output Module (IOM) 12b, and is also connected to a System Control Module (SCM) 13b and a Bus Exchange Module 23eb. Likewise in the second domain, the second domain main memory 15b is connected via a memory bus 16b to both the Bus Exchange Module (BEM) 12eb and the System Control Module (SCM) 13b which also has an arebitration circuit (ARBIT CKT) logic unit 13rb.
Now, again referring to FIG. 2, it will be noted that each Bus Exchange Module provides a link between the local bus 14a and the remote bus 14b. Further, for example, the Bus Exchange Module 23ea contains an address queue 23qa which has the purpose of accumulating Write-OP addresses which it has sensed as occurring on the remote bus 14b. At the appropriate time, these Write addresses can be transferred from the BEM 23ea over to the local bus 14a and loaded into the invalidation queue 11iqa for subsequent invalidation operations onto the cache 18a.
Now referrring to the Bus Exchange Module 23eb of the second domain 10b, it will be seen that the address queue 23qb is used to accumulate Write OP addresses occurring on the local bus 14a which can then be transferred on to the remote bus 14b for transfer and accumulation to the second domain invalidation queue 11iqb which can then perform invalidation operations in the second domain cache memory unit 18b.
Each of the Bus Exchange Modules 23ea and 23eb are also seen to contain Message Queues 21qa and 21qb which involve the storage of message which are being transferred between the local bus and the remote bus, or between the remote bus and the local bus, as the occasion requires.
As an example of the cross-linking between domains, it will be seen in FIG. 2 that the CPM 11a or the IOM 12a of the first domain may place a Write OP on the local SBUS 14a. This Write OP will be place in the Write OP address queue 23qb, which will then place it onto the second domain remote bus OSBUS 14b, from whence it can then be placed in the Snoop Invalidation Queue 11iqb in the second domain.
In the other direction, the Central Processing Module CPM 11b, or the Input/Output Module IOM 12b of the second domain, can initiate a Write OP onto the remote bus 14b, OSBUS which will then be placed into the Write OP address queue 23qa, which will then pass this information onto the local bus 14a., SBUS, and thence place the Write address into the Snoop Invalidation Queue 11iqa of the first domain.
In reguard to the Message Queues 21qa and 21qb, the following interlinking operations can occur. The CPM 11b and the IOM 12b of the second domain may pass a message on the remote bus 14b over into the message queue 21qa of the first domain, which can then pass the message onto the local bus 14a, SBUS, which can then convey the message over to the Central Processing Module CPM 11a or to the Input/Output Module IOM 12a of the first domain.
Similarly, going from the first domain to the second domain, the CPM 11a and the IOM 12a can place a message onto the local bus 14a, SBUS, which will then be conveyed to the second domain Bus Exchange Module BEM 23eb, which it is placed in the message queue 21qb. This is then conveyed onto the second domain remote bus 14b, OSBUS, and thence to the final target module which may be the CPM 11b or the IOM 12b, which may be the final destination modules for the message in the second domain, 10b.
Thus, the first domain modules, are operating to provide the appropriate priority of access (via the arbitration logic 13ra) to the first domain bus 14a while, at the same time, the first domain provides a Write OP Address Queue 23qa, and a Message Quenue 21qa which interlink with the second domain. Then also, the second domain using the Bus Exchange Module BEM 23eb, provides the Write OP Address Queue 23qb and the Message Queue 21qb which then provide an interlinking between the second domain and the first domain busses. Concurrently, the second domain System Control Module SCM 13b uses its arbitration logic (ABIR CKT) 13rb to determine which module will have priority of bus access to the second domain remote bus 14b (OSBUS).
When the Cental Processing Module, CPM 11a, of the first domain system 10a performs a Write operation with the Memory Module 15a of the same domain, then the busses and ports in the first domain 10a are used. Additionally, while the Write operation is being performed, the busses and ports are used to snoop or "spy" on the particular Write operation involved and subsequently used to invalidate any entry in the cache 18b of the second domain data processing system 10b, which corresponds to the new write entry made in the Memory Module 15a of the first domain system 10a that was being written to. As an example, if the entry at address 12345 is being written into the memory 15a of the first domain 10a, then also a message is sent via the busses and ports over to the cache 18b of the processing system of the second domain 10b, advising that the cache entry having that particular address 12345 should also be invalidated.
Another operational condition that can occur is where the Central Processing Module's CPM 11a of the first domain system 10a performs a Write operation on the Memory Module 15b of the second domain 10b. Again, the particular Write operation is performed by used of the busses and the ports. However, while that Write operation is being performed, the busses and ports are used to spy on this Write operation and thus to advise the cache 18b of the second domain Central Processing Module 10b to invalidate any cache entry in the cache 18b which corresponds to an entry in the Memory Module 15 b that is being Written into.
For brevity of discussion, sometimes the generalized number 11 will be used to designate the Central Processing Module, the generalized number 12 for the Input/Output Module, the generalized number 23 for the Bus Exchange Module, the generalized number 15 for the Main Memory Module and generalized number 13 for the System Control Module.
Another factor arise in that each of the so-called "Write" operations illustrated as being initiated by the Central Processing Module CPM 11, can also be initiated by the Input/Output Module IOM 12. In each of these cases, the data appears on the system bus 14 as originated from the Input/Output Module IOM 12, rather than from the Central Processing Module CPM 11.
In FIG. 2 it will be seen that the first domain Write OP address queue 23qa accumulates Write-address from the remote bus 14b of the second domain 10b and then sends the address onto the first domain local bus 14a, SBUS, which can then subsequently pass them onto the invalidation queue 11iqa for invalidation cycles into the cache memory 18a.
Likewise, the address queue 23qb in the second domain Bus Exchange Module 23eb, then also accumulates Write-addresses from the first domain local bus 14a and then sends them onto the second domain bus 14b (OSBUS) over to the second domain CPM 11b into the invalidation queue 11iqb for invalidation operations on the second domain cache memory 18b.
The presently described system uses an E-Mode protocol which involves blocks of four words which are transferred in sequence as a block of four words. E mode protocol is involved in Unisys A-Series processor architecture and is the interface between the machine and the program. It comprises a set of operator instructions and data types for communication between modules, and uses a 4-word block for data transfers. This 4-word protocol is described in U.S. Pat. No. 5,696,937.
Difficulties can arise in that the address queue, 23qa, which accumulates Write-OP addresses from the second domain remote bus 14b, OSBUS, can sometimes "lock-up" the bus 14a of the first domain, when there are long bursts of Write-OPs occurring on the bus 14b. In order to prevent such a locking-up of the bus 14a, the Bus Exchange Module, BEM, is generally given the "highest Priority" for access to the first domain local bus 14a, SBUS. But this occurs only during the time period the Bus Exchange Module is being "serviced", that is to say, if there should be occurring a request from the CPM 11a or from the IOM 12a, the arbiter (ARB) 13ra will then switch bus access priority of bus 14a over to the CPM 11a module or to the IOM 12a module thus stopping the flow of Write-address information from the second domain into the first domain.
The present system seeks to reduce the number of invalidation requests which can cause excess bus traffic leading to multiple "retry operations" which can then adversely affect the performance of the system. The retry operations occur when data is sought to be transmitted to a receiving module but the transmission could not be effectuated and must be repeated to try to reach the receiving module.
The present system addresses the situation of reducing the number of invalidation requests under certain conditions that occur so that the throughput of information transfer will not be adversely affected.